1. Field of the Invention
The present invention generally relates to a technology for a flip-flop circuit, and particularly relates to a flip-flop circuit having a majority-logic circuit for making it possible, even when a soft error takes place, to output correct storage contents and to recover from the soft error so as to maintain the correct storage contents.
2. Description of the Related Art
There is a phenomenon, known as a soft error, such that data maintained in a memory circuit, etc., are corrupted. The soft error is a phenomenon such that alpha rays generated from LSI-chip materials as well as secondary cosmic-ray neutrons causing electric charges to be generated within an electronic circuit influence one-bit data maintained in the memory circuit, or a flip-flop circuit within a logic-circuit section, to be reverted so as to corrupt the maintained data. When such soft error takes place, the memory circuit or the flip-flop circuit within the logic-circuit section malfunctioning does not mean, from the hardware point of view, that any failures have taken place in the malfunctioned memory circuit or the flip-flop circuit as described above. Therefore, if new data were written into the malfunctioned memory circuit or the flip-flop circuit as described above, the circuit should work as designed.
The soft error, typically taking place with a low probability as an isolated event, manifests itself as a fault with an even lower probability.
For example, an error-correction circuit is typically mounted in the memory circuit. Then, there is no influence of the one-bit error as described above at the output of the memory circuit as the one-bit error should be corrected by means of the error-correction circuit as described above.
Moreover, in the flip-flop circuit arranged within the logic-circuit section, writing is performed at a clock cycle immediately following the current clock cycle so that the corrupted data are maintained only for a short period, and the corrupted data are masked by other logic-circuit states so that the probability of the corrupted data not influencing the processing of other circuit sections is high.
On the other hand, as for some data such as parameter values of a timing-adjusting circuit, there is a high likelihood that an occurrence of the soft error as described above triggers malfunctioning across the whole chip. More specifically, data set during the period of an initializing operation of a system, etc., are not rewritten after the initializing is terminated for starting an actual operation, so that the corrupted data continue to be maintained, often resulting in a malfunction.
At the present, when the soft error as described above takes place, as for the flip-flop circuit for storing a signal which greatly influences the overall system, for example, triplicating a flip-flop to implement a three-input majority-logic circuit provides for reducing the probability of causing a fault to the system even when the soft error takes place.
FIG. 1 illustrates a conventional flip-flop circuit. In the flip-flop circuit as illustrated in FIG. 1, a flip-flop is triplicated to implement the three-input majority-logic circuit as described above. The flip-flop circuit as described above is primarily composed of a flip-flop 110, a flip-flop 120, a flip-flop 130, and a majority-logic circuit 140. The flip-flop 110 is composed of inverters 111 and 114, each with an enable terminal, and inverters 112, 113, 115, and 116. Input data 101 are supplied to the input of the inverter 111 with the enable terminal, while a clock signal (CK) 102 is supplied to the enable terminal of the inverter 111. The output of the inverter 111 is connected to the input of the inverter 112. The output of the inverter 112 is connected to the input of the inverter 113 and the input of the inverter 114. The output of the inverter 113 is connected to the input of the inverter 112. A clock signal (CKB) 103 is supplied to the enable terminal of the inverter 114. The output of the inverter 114 is connected to the input of the inverter 115. The output of the inverter 115 is connected to the input of the inverter 116, and one input of a two-input NAND circuit 141 and one input of a two-input NAND circuit 142 that are within the majority-logic circuit 140. The output of the inverter 116 is connected to the input of the inverter 115.
The majority-logic circuit 140 is composed of two-input NAND circuits 141 and 142 and 143, and a three-input NAND circuit 144. The outputs of the two-input NAND circuits 141, 142, and 143 are connected to the input of the three-input NAND circuit 144.
The flip-flop 120 in FIG. 1 is composed of inverters 121 through 126, while the flip-flop 130 is composed of inverters 131 through 136. The flip-flops 120 and 130 have the same configuration as the flip-flop 110. The output of the flip-flop 120 is connected to one input of the two-input NAND circuit 141 and one input of the two-input NAND circuit 143 that are within the majority-logic circuit 140, while the output of the flip-flop 130 is connected to one input of the two-input NAND circuit 142 and the one input of the two-input NAND circuit 143 that are within the majority-logic circuit 140.
The input data are supplied to the flip-flop 110 so that the supplied data are written into a master latch composed of the feedback inverters 112 and 113 when the clock signal 102 (CK) is at a low level and into a slave latch composed of the feedback inverters 115 and 116 when the clock signal 103 (CKB) is at a low level. For instance, the clock signal 102 (CK) and the clock signal 103 (CKB) may have their phases inverted from each other.
The flip-flops 120 and 130 are supplied the same input data 101 as the flip-flop 110 so as to perform the same operation.
The majority-logic circuit 140 outputs a logic level “1” as output data 104 when the logic level of at least two of the outputs of the flip-flops 110, 120 and 130 are “1”. On the other hand, the majority-logic circuit 140 outputs a logic level “0” as the output data 104 when the logic level of at least two of the outputs of the flip-flops 110, 120 and 130 are “0”.
However, a problem exists such that, for using the conventional flip-flop circuit as illustrated in FIG. 1, the size of the flip-flop circuit 100 is large. In addition, a problem exists such that, with a large number of flip-flops making up the flip-flop circuit 100, it takes a long time to test the flip-flop circuit 100 when implementing the flip-flop circuit 100 on a LSI circuit. Moreover, a problem exists such that, when the soft error takes place multiple times, the output of the conventional flip-flop circuit 100 as illustrated in FIG. 1 not having any functions of recovering from the soft error taking place becomes erroneous so as to cause a fault in the system in which the flip-flop circuit 100 is used.
Furthermore, the technology related to the present invention is also described in Patent Documents 1, 2, and 3:
Patent Document 1
JPO4-170792A
Patent Document 2
JP2002-185309A
Patent Document 3
JP61-256822A